1. Field of The Invention
This invention generally relates to a control system for controlling a cache memory and to a control system for controlling a cache tag memory. Further, this invention can be applied to a microprocessor having an address conversion device for translating logical addresses into physical addresses and a cache memory which is accessed by using physical addresses therein.
2. Description of The Related Art
Generally, the following measures are taken to realize a high-performance system:
(1) Improvement of performance of a microprocessor itself;
(2) Employment of parallel processing architecture;
(3) Employment of a multiprocessor architecture; and
(4) Provision of a large cache memory.
Especially, in case where the measures (3) and (4) are taken (namely, the multiprocessor architecture is employed and the large cache memory is provided), the system comes to be provided with a cache memory which is accessed by using physical addresses.
When a central processing unit (hereunder abbreviated as CPU) of the microprocessor accesses a cache memory by generating a logical address, it takes a period of time of one cycle in the address conversion device to translate the logical address to a physical address. Further, the cache memory is accessed by using the physical address generated in the address conversion device in the next one cycle and then the data is transferred to the CPU. In this case, it takes two or more cycles to obtain data or an instruction by accessing the cache memory after the CPU generates the logical address.
A high-performance microprocessor can be fully realized by effecting an access to the cache memory by using a physical address in one cycle. To this end, it is necessary to perform an access operation of the cache memory by using a physical address in parallel with an address conversion operation of translating a logical address to a physical address in one cycle. The present invention is created to resolve the above described problem.
It is accordingly an object of the present invention to provide control systems for controlling the cache memory and for controlling the cache tag memory, whereby an access operation of the cache memory by using a physical address can be performed in parallel with an address conversion operation of translating a logical address to a physical address in one cycle.